2-d material semiconductor device

ABSTRACT

A method includes forming a 2-D material semiconductor layer over a substrate; forming source/drain electrodes covering opposite sides of the 2-D material semiconductor layer, while leaving a portion of the 2-D material semiconductor layer exposed by the source/drain electrodes; forming a first gate dielectric layer over the portion of the 2-D material semiconductor layer by using a physical deposition process; forming a second gate dielectric layer over the first gate dielectric layer by using a chemical deposition process, in which a thickness of the first gate dielectric layer is less than a thickness of the second gate dielectric layer; and forming a gate electrode over the second gate dielectric layer.

PRIORITY CLAIM AND CROSS-REFERENCE

The present application is a Divisional application of U.S. applicationSer. No. 17/461,714, filed on Aug. 30, 2021, which is hereinincorporated by reference in their entirety.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapidgrowth. Technological advances in IC materials and design have producedgenerations of ICs. Each generation has smaller and more complexcircuits than the previous generation. However, these advances haveincreased the complexity of processing and manufacturing ICs.

In the course of IC evolution, functional density (i.e., the number ofinterconnected devices per chip area) has generally increased whilegeometric size (i.e., the smallest component (or line) that can becreated using a fabrication process) has decreased. This scaling-downprocess generally provides benefits by increasing production efficiencyand lowering associated costs.

However, since feature sizes continue to decrease, fabrication processescontinue to become more difficult to perform. Therefore, it is achallenge to form reliable semiconductor devices at smaller and smallersizes.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIGS. 1A to 5B are cross-sectional views of a memory device in variousstages of fabrication in accordance with some embodiments of the presentdisclosure.

FIG. 6 illustrates a method of forming a semiconductor device inaccordance with some embodiments of the present disclosure.

FIGS. 7A to 10B are cross-sectional views of a memory device in variousstages of fabrication in accordance with some embodiments of the presentdisclosure.

FIG. 11 illustrates a method of forming a semiconductor device inaccordance with some embodiments of the present disclosure.

FIGS. 12A to 18B are cross-sectional views of a memory device in variousstages of fabrication in accordance with some embodiments of the presentdisclosure.

FIG. 19 illustrates a method of forming a semiconductor device inaccordance with some embodiments of the present disclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

FIGS. 1A to 5B are cross-sectional views of a memory device in variousstages of fabrication in accordance with some embodiments of the presentdisclosure. Although the views shown in FIGS. 1A to 5B are describedwith reference to a method, it will be appreciated that the structuresshown in FIGS. 1A to 5B are not limited to the method but rather maystand alone separate of the method. Although FIGS. 1A to 5B aredescribed as a series of acts, it will be appreciated that these actsare not limiting in that the order of the acts can be altered in otherembodiments, and the methods disclosed are also applicable to otherstructures. In other embodiments, some acts that are illustrated and/ordescribed may be omitted in whole or in part.

Reference is made to FIGS. 1A and 1B, in which FIG. 1A is a perspectiveview of a semiconductor device, and FIG. 1B is a cross-sectional viewalong line B-B of FIG. 1A. An initial structure includes a substrate100. In some embodiments, the substrate 100 may function to providemechanical and/or structure support for features or structures that areformed in the subsequent steps of the process flow illustrated in FIGS.2A to 5B. These features or structures may be parts or portions of asemiconductor device (e.g. a transistor) that may be formed on or overthe substrate 100.

The substrate 100 may be a semiconductor substrate. For example, thesubstrate 100 may include sapphire (e.g. crystalline Al₂O₃), e.g. alarge grain or a single crystalline layer of sapphire or a coating ofsapphire. As another example, the substrate 100 may be a sapphiresubstrate, e.g. a transparent sapphire substrate comprising, as anexample, α-Al₂O₃. Other elementary semiconductors like germanium mayalso be used for substrate 100. Alternatively or additionally, substrate100 includes a compound semiconductor such as silicon carbide, galliumarsenide, indium arsenide, indium gallium arsenide (InGaAs) and/orindium phosphide. Further, substrate 100 may also include asilicon-on-insulator (SOI) structure. Substrate 100 may also be othersuitable substrates, which are all included in the disclosure andnon-limiting. Substrate 100 may include an epitaxial layer and/or may bestrained for performance enhancement. Substrate 100 may also includevarious doping configurations depending on design requirements, such asp-type substrate and/or n-type substrate and various doped regions suchas p-wells and/or n-wells.

A 2-D material layer 110 is formed over the substrate 100. In someembodiments, the 2-D material layer 110 is in direct contact with thetop surface of the substrate 100. As used herein, consistent with theaccepted definition within solid state material art, a “2-D material”may refer to a crystalline material consisting of a single layer ofatoms. As widely accepted in the art, “2-D material” may also bereferred to as a “monolayer” material. In this disclosure, “2-Dmaterial” and “monolayer” material are used interchangeably withoutdifferentiation in meanings, unless specifically pointed out otherwise.

The 2-D material layer 110 may be 2-D materials of suitable thickness.In some embodiments, a 2-D material includes a single layer of atoms ineach of its monolayer structure, so the thickness of the 2-D materialrefers to a number of monolayers of the 2-D material, which can be onemonolayer or more than one monolayer. The coupling between two adjacentmonolayers of 2-D material includes van der Waals forces, which areweaker than the chemical bonds between/among atoms within the singlemonolayer.

Formation of the 2-D material layer 110 may include suitable processesdepending on the 2-D material layer 110 and the substrate 100. In someembodiments, the 2-D material layer 110 includes a transition metaldichalcogenide (TMD) monolayer material. In some embodiments, a TMDmonolayer includes one layer of transition metal atoms sandwichedbetween two layers of chalcogen atoms. Substrate 100 may include anysubstrates that are suitable for the formation of the TMD monolayersthereover. For example, substrate 100 may be selected based on itscapacity to sustain the potential high temperature in the formation ofthe TMD monolayers thereover. In some embodiments, a sapphire substrate100 is used.

In some embodiment where the 2-D material layer 110 is TMD monolayers,the TMD monolayers include molybdenum disulfide (MoS₂), tungstendisulfide (WS₂), tungsten diselenide (WSe₂), or the like. In someembodiments, MoS₂ and WS₂ may be formed on the substrate 100, e.g., asapphire substrate, using suitable approaches. For example, MoS₂ and WS₂may be formed by micromechanical exfoliation and coupled over thesubstrate 100, or by sulfurization of a pre-deposited molybdenum (Mo)film or tungsten (W) film over the substrate 100. In alternativeembodiments, WSe₂ may be formed by micromechanical exfoliation andcoupled over the substrate 100, or by selenization of a pre-depositedtungsten (W) film over the substrate 100 using thermally cracked Semolecules.

In some embodiments, forming of the 2-D material layer 110 also includestreating the 2-D material layer 110 to obtain expected electronicproperties of the 2-D material layer 110. The treating processes includethinning (namely, reducing the thickness of the 2-D material layer 110),doping, or straining, to make the 2-D material layer 110 exhibit certainsemiconductor properties, e.g., including direct bandgap. The thinningof the 2-D material layer 110 may be achieved through various suitableprocesses, and all are included in the present disclosure. For example,plasma based dry etching, e.g., reaction-ion etching (RIE), may be usedto reduce the number of monolayers of the 2-D material layer 110.

In the description hereinafter, the 2-D material layer 110 may includesemiconductor properties (interchangeably referred to as semiconductor2-D material layer in this context). In some embodiments, each monolayerof MoS₂ is about 6.5 angstrom (Å) to about 7.5 Å in thickness (e.g., 7.0Å) in thickness. In some embodiments, the thickness of the MoS₂ 2-Dmaterial layer 110 is in a range from about 0.7 nm to about 7 nm, namelyabout 1 to about 10 monolayers of MoS₂. In some embodiments, eachmonolayer of WSe₂ is about 6.5 angstrom (Å) to about 7.5 Å in thickness(e.g., 7.0 Å) in thickness. In some embodiments, the thickness of theWSe₂2-D material layer 110 is in a range from about 0.7 nm to about 7nm, namely about 1 to about 10 monolayers of WSe₂.

Reference is made to FIGS. 2A and 2B, in which FIG. 2A is a perspectiveview of a semiconductor device, and FIG. 2B is a cross-sectional viewalong line B-B of FIG. 2A. Source/drain metals 120 are formed onopposite sides of the 2-D material layer 110. In some embodiments, eachof the source/drain metals 120 includes a first metal layer 120A and asecond metal layer 120B over the first metal layer 120A. In someembodiments, portions of the 2-D material layer 110 covered by thesource/drain metals 120 can be referred to as source/drain regions110SD, and a portion of the 2-D material layer 110 between thesource/drain metals 120 (or the source/drain regions 110SD) can bereferred to as channel region 110CH. The source/drain metals 120 may beformed through sputtering or other suitable processes like CVD, PVD,plating, or other suitable process.

In some embodiments, the first metal layer 120A may serve as aseparation metal layer, which is used to separate the 2-D material layer110 from the second metal layer 120B, such that the second metal layer120B would not contact the 2-D material layer 110. In some embodimentswhere the first metal layer 120A is omitted, the 2-D material layer 110would be in contact with the second metal layer 120B. In that scenario,the second metal layer 120B may form alloy with the 2-D material layer110 during deposition of the second metal layer 120B, which mightdeteriorate the 2-D crystal structure of the 2-D material layer 110.Accordingly, the material of the first metal layer 120A is selected suchthat the material would not form an alloy with the 2-D material layer110. In some embodiments, the first metal layer 120A may include metalsuch as gold (Au), aluminum (Al), bismuth (Bi), cadmium (Cd), chromium(Cr), iridium (Ir), niobium (Nb), tantalum (Ta), tellurium (Te),tungsten(W), or other suitable metal.

In some embodiments, the second metal layer 120B may be formed ofsuitable electrically conductive material, including poly silicon,graphene, and metal including one or more layers of aluminum (Al),copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co),molybdenum (Mo), nickel (Ni), manganese (Mg), silver (Ag), palladium(Pd), rhenium (Re), iridium (Ir), ruthenium (Ru), platinum (Pt),zirconium (Zr), tantalum nitride (TaN), nickel silicide (NiSi), cobaltsilicide (CoSi), TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys,other suitable materials, and/or combinations thereof.

In some embodiments, the area of each of the source/drain metals 120 isabout 80×80 μm². In some embodiments, the first metal layer 120A of thesource/drain metals 120 may be gold (Au) having a thickness in a rangefrom about 90 nm to about 110 nm (e.g., about 100 nm in someembodiments). In some embodiments, the second metal layer 120B of thesource/drain metals 120 may be titanium (Ti) having a thickness in arange from about 8 nm to about 12 nm (e.g., about 10 nm in someembodiments). In some embodiments, the first metal layer 120A is thickerthan the second metal layer 120B, ensuring that the second metal layer120B would not form alloy with the 2-D material layer 110. For example,the ratio of the first metal layer 120A to the second metal layer 120Bmay be in a range from about 9 to 14. In some embodiments, the firstmetal layer 120A is made of Au and the second metal layer 120B is madeof Ti, and the thickness of the first metal layer 120A is about 100 nmand the thickness of the second metal layer 120B is about 10 nm.

In some embodiments, the source/drain metals 120 may be formed by, forexample, depositing a photoresist layer over the substrate 100 bysuitable process, such as spin-coating technique, which may includebaking the photoresist layer after coating. The photoresist layer mayinclude positive-type or negative-type resist materials. For example,the photoresist layer include poly(methylmethacrylate) (PMMA). Then, thephotoresist layer is subjected to an exposure process. Afterward, thephotoresist layer is developed by a suitable process. For example, thephotoresist layer is exposed to a developing solution, such astetramethylammonium hydroxide (TMAH), to remove portions of thephotoresist layer to form the openings that expose the source/drainregions 110SD of the 2-D material layer 110. Next, a first conductivematerial of the first metal layer 120A and a second conductive materialof the second metal layer 120B are sequentially deposited over thesubstrate 100 by suitable process, such as thermal evaporation,sputtering, PVD, or the like. Afterward, portions of the firstconductive material and the second conductive material over the topsurface of the photoresist layer are lifted off together with thephotoresist layer, such that other portions of the first conductivematerial and the second conductive material in the openings remain overthe substrate 100. The remaining portions of the first conductivematerial and the second conductive material denote the first metal layer120A and the second metal layer 120B of the source/drain metals 120,respectively. In some other embodiments, the source/drain metals 120 maybe formed by, for example, depositing a first conductive material of thefirst metal layer 120A and a second conductive material of the secondmetal layer 120B are sequentially deposited over the substrate 100, andperforming a patterning process to remove unwanted portions of the firstconductive material and the second conductive material. The remainingportions of the first conductive material and the second conductivematerial denote the first metal layer 120A and the second metal layer120B of the source/drain metals 120, respectively.

Reference is made to FIGS. 3A and 3B, in which FIG. 3A is a perspectiveview of a semiconductor device, and FIG. 3B is a cross-sectional viewalong line B-B of FIG. 3A. A dielectric layer 130 is formed over thesubstrate 100. In some embodiments, the dielectric layer 130 extendsalong the top surface of the substrate 100, sidewalls and top surfacesof the source/drain metals 120, and the top surface of the channelregion 110CH of the 2-D material layer 110. In some embodiments, thedielectric layer 130 includes a portion 130CH in contact with thechannel region 110CH of the 2-D material layer 110, and the portion130CH may serve as a gate dielectric layer in the final structure.Accordingly, the portion 130CH of the dielectric layer 130 mayinterchangeably referred to as gate dielectric layer 130CH in thiscontext. In some embodiments, the dielectric layer 130 may be formed ofaluminum oxide (Al₂O₃), while other suitable gate dielectric materialmay also be employed. For example, the dielectric layer 130 may includehigh-k dielectrics, such as TiO₂, HfZrO, Ta₂O₃, HfSiO₄, ZrO₂, ZrSiO₂,LaO, AlO, ZrO, TiO, Ta₂O₅, Y₂O₃, SrTiO₃ (STO), BaTiO₃ (BTO), BaZrO,HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO₃ (BST),Al₂O₃, Si₃N₄, oxynitrides (SiON), combinations thereof, or othersuitable material.

In some embodiments, the dielectric layer 130 is formed by atomic layerdeposition (ALD) process. An ALD process may include growing a film(s)(e.g., the dielectric layer 130) by exposing a wafer (e.g., substrate100) to alternating pulses (e.g., short introductions of vapor) ofcomponents, for example, a precursor and a co-reactant. The pulses mayinclude self-limiting reactions and result in the deposition of a filmand/or the chemisorbing of one or more components. Each pulse may beseparated by an inert gas purge of an ALD chamber.

Reference is made to FIGS. 3A, 3B, and 6 , in which FIG. 6 illustratessteps of an ALD cycle of an ALD process in accordance with someembodiments of the present disclosure. As an example where thedielectric layer 130 is made of aluminum oxide (Ak₂O₃), each ALD cycleincludes steps S11, S12, S13, S14, and S15.

The ALD cycle starts from step S11 with a first pulse providing a firstprecursor. In some embodiments, the first precursor may include a sourceof oxygen, such as H₂O. In some embodiments, H₂O is pulsed into the ALDchamber where the wafer is placed. The water vapor may be attracted onexposed surface of the wafer (e.g., exposed surfaces of the 2-D materiallayer 110, the source/drain metals 120, and the substrate 100). Here,the term “first pulse” may be referred to a duration from the start ofinjection of the first precursor to the halt of injection of the firstprecursor. In some embodiments, the time duration of the first pulse isin a range from about 20 ms to about 100 ms.

The ALD cycle proceeds to step S12 with a first purging process. Afterthe first pulse providing the first precursor, the ALD process mayinclude a first purging process for purging excess first precursor. Insome embodiments, the purging gas may be N₂, Ar, He, or similar inertgases.

The ALD cycle proceeds to step S13 with a second pulse providing asecond precursor. In some embodiments, the second precursor may includea source of aluminum, such as trimethyl aluminum (denoted AlMe₃,Al(CH₃)₃, or TMA). The functional groups of the second precursor (e.g.,TMA) react with the functional groups of the first precursor (e.g., H₂O)to form Al—O bonds, thereby forming a monolayer of Al₂O₃. Here, the term“second pulse” may be referred to a duration from the start of injectionof the second precursor to the halt of injection of the secondprecursor. In some embodiments, the time duration of the second pulse isin a range from about 10 ms to about 50 ms.

The ALD cycle proceeds to step S14 with an additional stay time forsecond precursor. In some embodiments, after the second pulse providingthe second precursor (or after halting the injection of the secondprecursor), the wafer (e.g., exposed surfaces of the 2-D material layer110, the source/drain metals 120, and the substrate 100) is kept exposedto a gas environment of the second precursor in the ALD chamber for anon-zero time duration. That is, excess second precursor is not purgedaway immediately after the second pulse. Because the surface of the 2-Dmaterial layer 110 lacks dangling bonds to provide nucleation sites forthe dielectric layer 130, this will result in a weak adhesion betweenthe dielectric layer 130 and the 2-D material 110 layer. Accordingly,the additional stay time (or call soaking time) may help the secondprecursor to uniformly distribute over the surface of the 2-D material110, and thus the uniformity of the dielectric layer 130 may beimproved, which will also improve the device performance.

In some embodiments, the additional stay time is in a range from about10 ms to about 40 ms. For example, the additional stay time may be about20 ms in some embodiments. If the additional stay time is too short, thesecond precursor may not uniformly distribute over the surface of the2-D material 110, and will leads to a poor uniformity of the dielectriclayer 130. If the additional stay time is too long, it may not furtherimprove the quality of the dielectric layer 130.

In some embodiments, there is no additional stay time between steps S11and S12. That is, the first purging process is performed immediatelyafter the first pulse of the first precursor (or after the halting theinjection of the first precursor) with substantially zero time delay. Insome other embodiments, there may be a stay time between the first pulseof the first precursor and the first purging process, while the staytime between the first pulse of the first precursor and the firstpurging process is less than the stay time (e.g., step S14) between thesecond pulse of the second precursor and the second purging process.

The ALD cycle proceeds to step S15 with a second purging process. Afterthe second pulse providing the second precursor, the ALD process mayinclude a second purging process for purging excess second precursor. Insome embodiments, the purging gas may be N₂, Ar, He, or similar inertgases.

According to the aforementioned discussion, each ALD cycle of the ALDprocess for forming the dielectric layer 130 may include sequentiallyperforming steps S11, S12, S13, S14, and S15 in FIG. 6 . The ALD processmay include performing the ALD cycle for several times to obtain adesired thickness of the dielectric layer 130 over the 2-D materiallayer 110. In some embodiments, the ALD process may include performingthe ALD cycle for about 10 times to about 100 times. Accordingly, thethickness of the dielectric layer 130 may be in a range from about 5 nmto about 30 nm. For example, the dielectric layer 130 may be about 10 nmin some embodiments. If the dielectric layer 130 is too thin, dielectriclayer 130 may have poor coverage over the 2-D material layer 110. If thedielectric layer 130 is too thick, the device performance may beunsatisfied due to thick gate dielectric layer.

In some embodiments, the ALD process may be performed under atemperature in a range from about 150° C. to about 180° C. If thetemperature is too low, the dielectric layer 130 may not have goodquality, for example, Al₂O₃ grains may be formed on the surface of the2-D material layer 110. If the temperature is too high, it may inverselyaffect other components over the substrate 100.

Reference is made to FIGS. 4A and 4B, in which FIG. 4A is a perspectiveview of a semiconductor device, and FIG. 4B is a cross-sectional viewalong line B-B of FIG. 4A. A gate electrode 140 is formed over thedielectric layer 130. In some embodiments, the gate electrode 140 mayinclude a first metal layer and a second metal layer over the firstmetal layer. The gate electrode 140 may vertically overlaps an entiretyof the channel region 110CH of the 2-D material layer 110. In someembodiments, the gate electrode 140 at least vertically overlapsportions of the source/drain metals 120 and portions of the source/drainregions 110SD of the 2-D material layer 110.

In some embodiments, the first metal layer may include metal such asgold (Au), aluminum (Al), bismuth (Bi), cadmium (Cd), chromium (Cr),iridium (Ir), niobium (Nb), tantalum (Ta), tellurium (Te), tungsten(W),or other suitable metal. In some embodiments, the second metal layer maybe formed of suitable electrically conductive material, includingpolysilicon, graphene, and metal including one or more layers ofaluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W),cobalt (Co), molybdenum (Mo), nickel (Ni), manganese (Mg), silver (Ag),palladium (Pd), rhenium (Re), iridium (Ir), ruthenium (Ru), platinum(Pt), zirconium (Zr), tantalum nitride (TaN), nickel silicide (NiSi),cobalt silicide (CoSi), TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metalalloys, other suitable materials, and/or combinations thereof. In someembodiments, the first metal layer of the gate electrode 140 may be gold(Au) having a thickness in a range from about 90 nm to about 110 nm(e.g., about 100 nm in some embodiments). In some embodiments, thesecond metal layer of the gate electrode 140 may be titanium (Ti) havinga thickness in a range from about 8 nm to about 12 nm (e.g., about 10 nmin some embodiments). In some embodiments, the first metal layer isthicker than the second metal layer. In some embodiments, the formationmethod of the gate electrode 140 may be similar to those described withrespect to the source/drain metals 120, and thus relevant details willnot be repeated for simplicity.

Reference is made to FIGS. 5A and 5B, in which FIG. 5A is a perspectiveview of a semiconductor device, and FIG. 5B is a cross-sectional viewalong line B-B of FIG. 5A. An interlayer dielectric (ILD) layer 150 andinterconnection structures 160 are formed. At least two of theinterconnection structures 160 penetrate through the ILD layer 150 anddielectric layer 130 and are electrically connected to and in contactwith respective source/drain metals 120, and at least one of theinterconnection structures 160 is electrically connected to and incontact with the gate electrode 140.

In some embodiments, the interlayer dielectric (ILD) layer 150 may beformed by suitable deposition process, such as CVD, PVD, ALD, or thelike. Next, openings are forming in the ILD layer 150. Conductivematerial is formed in the openings followed by a CMP process to removeexcess conductive material to form the interconnection structures 160.In some embodiments, the ILD 150 may be silicon oxide or a low-Kdielectric material. The interconnection structures 160 may be copperCu, cobalt Co, tungsten W or aluminum Al or other suitable conductivematerials. In an embodiment, the interconnection structures 160 areformed through the ILD 150 using a damascene process.

In some embodiments of the present disclosure, by employing anadditional stay time for a precursor in an ALD cycle for forming anoxide layer over a 2-D material surface, and by forming the oxide layerwith a greater thickness, the uniformity of the oxide layer over the 2-Dmaterial surface can be improved. Accordingly, the device performancemay be improved.

FIGS. 7A to 10B are cross-sectional views of a semiconductor device invarious stages of fabrication in accordance with some embodiments of thepresent disclosure. It is noted that some elements discussed in FIGS. 7Ato 10B are similar or the same as those discussed in FIGS. 1A to 6 ,such elements are labeled the same and relevant details will not berepeated for simplicity.

Reference is made to FIGS. 7A and 7B, in which FIG. 7A is a perspectiveview of a semiconductor device, and FIG. 7B is a cross-sectional viewalong line B-B of FIG. 7A. The structure of FIGS. 7A and 7B follows thestructure shown in FIGS. 2A and 2B where a dielectric layer 135 isformed over the substrate 100. In some embodiments, the dielectric layer135 extends along the top surface of the substrate 100, sidewalls andtop surfaces of the source/drain metals 120, and the top surface of thechannel region 110CH of the 2-D material layer 110. In some embodiments,the dielectric layer 135 may be formed of aluminum oxide (Al₂O₃), whileother suitable gate dielectric material may also be employed.

In some embodiments, the dielectric layer 135 may be formed by aphysical deposition process, such as thermal evaporation, electron beam(e-beam) evaporation, RF sputtering, pulsed laser deposition (PLD), andother suitable techniques. In a physical deposition process, thematerial to be deposited starts out as a solid and is transported to asurface (e.g., the 2-D material layer 110) where a film is slowly builtup. For example, in e-beam evaporation, an electron beam is used as apower source to heat the target source to produce vaporized materialsand condense on substrates. In RF sputtering, source materials areejected from the target source and deposited on the substrate by usingRF source to increase concentration of electron ionizations and lengthsof electron paths thus increasing the ionization efficiency. In pulsedlaser deposition (PLD), a high-power pulsed laser beam is focused insidea chamber to strike the target source of the material that is to bedeposited.

Reference is made to FIGS. 8A and 8B, in which FIG. 8A is a perspectiveview of a semiconductor device, and FIG. 8B is a cross-sectional viewalong line B-B of FIG. 8A. A dielectric layer 130 is formed over thedielectric layer 135. The formation of the dielectric layer 130 issimilar to those discussed with respect to FIGS. 3A, 3B, and 6 , andthus relevant details will not be repeated for simplicity. Afterward, aportion of the dielectric layer 135 and a portion of the dielectriclayers 130 over the channel region 110CH of the 2-D material layer canbe collectively referred to as gate dielectric 136 in the finalstructure. In some embodiments, the dielectric layer 130 and thedielectric layer 135 are made of the same material, such as aluminumoxide (Al₂O₃). In some other embodiments, the dielectric layer 130 andthe dielectric layer 135 are made of different materials. For example,the dielectric layer 130 and the dielectric layer 135 may include mayinclude high-k dielectrics, such as TiO₂, HfZrO, Ta₂O₃, HfSiO₄, ZrO₂,ZrSiO₂, LaO, AlO, ZrO, TiO, Ta₂O₅, Y₂O₃, SrTiO₃ (STO), BaTiO₃ (BTO),BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO₃(BST), Al₂O₃, Si₃N₄, oxynitrides (SiON), combinations thereof, or othersuitable material.

As mentioned above, the dielectric layer 135 is formed by a physicaldeposition. However, the dielectric layer 130 is formed by a chemicaldeposition, such as the ALD process discussed in FIGS. 3A, 3B, and 6 .Here, the term “physical deposition” may refer to a deposition of filmthat is done by transporting a material from a target source to asubstrate (e.g., the substrate 100). On the other hand, the term“chemical deposition” may refer to a deposition of film that is done bychemical reaction between at least two precursors injected into thechamber.

As mentioned above, the surface of the 2-D material layer 110 lacksdangling bonds to provide nucleation sites for the dielectric materialsof the dielectric layers 130 and 135. If the dielectric material (e.g.,Al₂O₃) is formed by a chemical deposition, such as ALD process, theprecursors may be hard to uniformly distribute over the surface of the2-D material layer 110. However, due to the nature of physicaldeposition, the vaporized materials or ionized materials may be “droppedover” the surface of the 2-D material layer 110, and may include bettercoverage over the 2-D material layer 110 than using a chemicaldeposition. Accordingly, the thin film of dielectric layer 135 formed byphysical deposition may act as a seed layer for the following depositeddielectric layer 130, and the composite layer of the dielectric layers130 and 135 may have better coverage and uniformity over the 2-Dmaterial layer 110.

In some embodiments of the present disclosure, using a pre-oxidedeposition to form an oxide layer (e.g., the dielectric layer 135) mayimprove the coverage of the composite dielectric layer (e.g., thedielectric layers 135 and 130) over a 2-D material surface. Furthermore,by combining a physical deposition and a chemical deposition, it ispossible to avoid the issue of precursor distribution on a 2-D materialsurface with the help of physically deposited thin oxide layer, andstill obtain a flat dielectric layer through the chemical deposition. Inthis way, the device performance may be improved. For example, the gateleakage currents may be suppressed.

In some embodiments, the dielectric layer 130 is thicker than thedielectric layer 135. In some embodiments, the thickness of thedielectric layer 135 may be in a range from about 1 nm to about 10 nm.For example, the dielectric layer 135 may be about 5 nm in someembodiments. In some embodiments, the dielectric layer 130 may be in arange from about 5 nm to about 30 nm. For example, the dielectric layer135 may be about 20 nm in some embodiments. In some embodiments, thetotal thickness of the dielectric layers 135 and 130 may be in a rangefrom about 20 nm to about 30 nm. For example, the total thickness of thedielectric layers 135 and 130 may be about 25 nm in some embodiments.

Reference is made to FIGS. 9A and 9B, in which FIG. 9A is a perspectiveview of a semiconductor device, and FIG. 9B is a cross-sectional viewalong line B-B of FIG. 9A. A gate electrode 140 is formed over thedielectric layer 130.

Reference is made to FIGS. 10A and 10B, in which FIG. 10A is aperspective view of a semiconductor device, and FIG. 10B is across-sectional view along line B-B of FIG. 10A. An interlayerdielectric (ILD) layer 150 and interconnection structures 160 areformed. At least two of the interconnection structures 160 penetratethrough the ILD layer 150 and dielectric layers 130, 135 and areelectrically connected to and in contact with respective source/drainmetals 120, and at least one of the interconnection structures 160 iselectrically connected to and in contact with the gate electrode 140.

FIG. 11 illustrates a method M1 of forming a semiconductor device inaccordance with some embodiments of the present disclosure. Although themethod M1 is illustrated and/or described as a series of acts or events,it will be appreciated that the method is not limited to the illustratedordering or acts. Thus, in some embodiments, the acts may be carried outin different orders than illustrated, and/or may be carried outconcurrently. Further, in some embodiments, the illustrated acts orevents may be subdivided into multiple acts or events, which may becarried out at separate times or concurrently with other acts orsub-acts. In some embodiments, some illustrated acts or events may beomitted, and other un-illustrated acts or events may be included.

At step S101, a 2-D material layer is formed over a substrate. FIGS. 1Aand 1B illustrate a perspective view and a cross-sectional view of someembodiments corresponding to act in step S101.

At step S102, source/drain metals are formed over the 2-D materiallayer. FIGS. 2A and 2B illustrate a perspective view and across-sectional view of some embodiments corresponding to act in stepS102.

At step S103, a first dielectric layer is formed over the substrate byusing a physical deposition. FIGS. 7A and 7B illustrate a perspectiveview and a cross-sectional view of some embodiments corresponding to actin step S103.

At step S104, a second dielectric layer is formed over the substrate byusing a chemical deposition. FIGS. 3A, 3B, 8A and 8B illustrate aperspective view and a cross-sectional view of some embodimentscorresponding to act in step S104.

At step S105, a gate electrode is formed over the second dielectriclayer. FIGS. 4A, 4B, 9A and 9B illustrate a perspective view and across-sectional view of some embodiments corresponding to act in stepS105.

At step S106, an ILD layer and interconnection structures are formedover the substrate. FIGS. 5A, 5B, 10A and 10B illustrate a perspectiveview and a cross-sectional view of some embodiments corresponding to actin step S106.

FIGS. 12A to 18B are cross-sectional views of a memory device in variousstages of fabrication in accordance with some embodiments of the presentdisclosure. It is noted that some elements discussed in FIGS. 12A to 18Bare similar or the same as those discussed in FIGS. 1A to 10B, suchelements are labeled the same and relevant details will not be repeatedfor simplicity.

Reference is made to FIGS. 12A and 12B, in which FIG. 12A is aperspective view of a semiconductor device, and FIG. 12B is across-sectional view along line B-B of FIG. 12A. A 2-D material layer110 is formed over a substrate 100.

Reference is made to FIGS. 13A and 13B, in which FIG. 13A is aperspective view of a semiconductor device, and FIG. 13B is across-sectional view along line B-B of FIG. 13A. A 2-D material layer115 is formed over the 2-D material layer 110. In some embodiments, the2-D material layer 115 is selective grown on the 2-D material layer 110.Because the 2-D material layer 115 is selectively formed over the 2-Dmaterial layer 110 sidewalls of the 2-D material layer 115 may becoterminous with respective sidewalls of the 2-D material layer 110. Insome embodiments, the 2-D material layer 115 may include antimonene,graphene, germanene, stanene, or the like. Specifically, antimonene isthe 2-D allotrope of antimony (Sb), germanene is the 2-D allotrope ofgermanium (Ge), and stanene is the 2-D allotrope of tin (Sn),respectively.

The 2-D material layer 115 is different from the 2-D material layer 110at least in the composition. The 2-D material layer 115 may be suitable2D material and may be deposited using processes suitable for the 2-Dmaterial layer 115. In an example, the 2-D material layer 115 may beformed with a semimetal electronic property or may be treated to exhibita semimetal property. As used herein, a semimetal electronic property(“semimetal property”) refers to an absence of a bandgap and anegligible density of states at the Fermi level. A semimetal material ora semimetal state of a material has both holes and electrons thatcontribute to electrical conduction and is conductive. On the otherhand, the 2-D material layer 110 may be formed with semiconductorproperties.

In some embodiments where the 2-D material layer 115 is made ofantimonene (Sb), the 2-D material layer 115 may be grown over the 2-Dmaterial layer 110 using thermal evaporation, molecular beam epitaxy(MBE) or physical vapor deposition (PVD) processes with a growthtemperature ranging from 100° C. to about 150° C. (e.g., about 120° C.)for a time duration ranging from about 10 seconds to about 600 seconds.This growth temperature range supports the selective growth of theantimonene over the 2-D material layer 110 without formation ofantimonene over the exposed surface of the substrate 100. As such, thedeposition of the antimonene precursors may be globally conducted overthe whole surface of the substrate 100 without differentiation betweenthe 2-D material layer 110 and the surface of the substrate 100. Withthe controlled growth temperatures within 150° C. to about 300° C., theselective growth of the antimonene layer 115 only over the 2-D materiallayer 110 may be achieved. In some embodiments, with the 2-D materiallayer 115 formed satisfactorily, the 2-D material layer 115 may followthe pattern of the 2-D material layer 110. That is, the 2-D materiallayer 115 may completely overlap the 2-D material layer 110.

In some embodiments, the 2-D material layer 115 may be treated so thatit exhibits the desired electronic properties. For example, a thicknessof 2-D material layer 115 is controlled such that the 2-D material layer115 exhibits electronic properties suitable for the design andapplication requirements. In an example, the thickness of the 2-Dmaterial layer 115 may be controlled by adjusting the time duration ofthe growth process, e.g., the MBE and/or the TBC procedures. Forexample, a longer MBE process will produce a thicker 2-D material layer115 initially, namely more layers of monolayer. The thickness may befurther controlled by a thinning process to reduce the number ofmonolayers of the 2-D material layer 115, such as by plasma-based dryetching, e.g., a reactive-ion etching. In some embodiments, thethickness of the 2-D material layer 115 may be in a range from about 90nm to about 110 nm. For example, the thickness of the 2-D material layer115 may be about 100 nm in some embodiments.

Reference is made to FIGS. 14A and 14B, in which FIG. 14A is aperspective view of a semiconductor device, and FIG. 14B is across-sectional view along line B-B of FIG. 14A. Source/drain metals 120are formed on opposite sides of the 2-D material layer 115, whileexposing a center portion of the 2-D material layer 115. In someembodiments, the source/drain metals 120 extend from the top surface ofthe 2-D material layer 115, along the sidewalls of the 2-D materiallayers 115, 110, to a top surface of the substrate 100.

The source/drain metals 120 may be gold (Au), tungsten (W), cobalt (Co)or other suitable metal/conductive materials for terminal electrodes.Other suitable metal/conductive materials for terminal electrodesinclude ruthenium, palladium, platinum, nickel, and/or conductive metaloxides and other suitable materials for P-type metal materials, and mayinclude hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta),aluminum (Al), aluminides and/or conductive metal carbides (e.g.,hafnium carbide, zirconium carbide, titanium carbide, and aluminumcarbide), and other suitable materials. The formation and the materialsof the source/drain metals 120 may be similar or the same as thesource/drain metals 120 described in FIGS. 2A and 2B, and thus relevantdetails will not be repeated for simplicity.

Reference is made to FIGS. 15A and 15B, in which FIG. 15A is aperspective view of a semiconductor device, and FIG. 15B is across-sectional view along line B-B of FIG. 15A. The 2-D material layer115 (see FIGS. 14A and 14B) is patterned by using the source/drainmetals 120 as a hard mask (etching mask). In greater detail, the 2-Dmaterial layer 115 exposed by the source/drain metals 120 are removed,and the remaining portions of the 2-D material layer 115 denote the 2-Dmaterial layers 116. In some embodiments, the 2-D material layer 115 maypatterned by using etching process, the etching is selective withrespect to the portions of the 2-D material layer 115 underlying thesource/drain metals 120. In some embodiments, the etching process mayinclude dipping the structure over the substrate 100 into a basicsolution, such as potassium hydroxide (KOH) solution, sodium hydroxide(NaOH) solution, for about 50 sec to about 70 sec (e.g., 60 sec).

In some embodiments, the 2-D material layers 116 and the source/drainmetals 120 may collectively serve as source/drain electrode in the finalstructure. In some embodiments, each of the 2-D material layers 116 isthinner than the source/drain metals 120.

Reference is made to FIGS. 16A and 16B, in which FIG. 16A is aperspective view of a semiconductor device, and FIG. 16B is across-sectional view along line B-B of FIG. 16A. A dielectric layer 135is formed over the substrate 100. In some embodiments, the dielectriclayer 135 is in contact with the top surface of the 2-D material layer110, sidewalls of the 2-D material layers 116, and sidewalls of thesource/drain metals 120.

Reference is made to FIGS. 17A and 17B, in which FIG. 17A is aperspective view of a semiconductor device, and FIG. 17B is across-sectional view along line B-B of FIG. 17A. A dielectric layer 130is formed over the dielectric layer 135.

Reference is made to FIGS. 18A and 18B, in which FIG. 18A is aperspective view of a semiconductor device, and FIG. 18B is across-sectional view along line B-B of FIG. 18A. A gate electrode 140 isformed over the dielectric layer 135, and an interlayer dielectric (ILD)layer 150 and interconnection structures 160 are formed.

In some embodiments of the present disclosure, by forming a 2-D materialconductive layer serving as source/drain electrode over a 2-D materialsemiconductor layer, the contact resistance between the 2-D materialsemiconductor layer and the source/drain electrode may be reduced, whichwill improve the device performance. For example, the drain current ofthe device under V_(DS)=2V may increases to about 4×10⁴ μA. Also,leakage current between the source/drain electrodes may also be reduced,which will increase the On/Off ratio of the device.

FIG. 19 illustrates a method M2 of forming a semiconductor device inaccordance with some embodiments of the present disclosure. Although themethod M2 is illustrated and/or described as a series of acts or events,it will be appreciated that the method is not limited to the illustratedordering or acts. Thus, in some embodiments, the acts may be carried outin different orders than illustrated, and/or may be carried outconcurrently. Further, in some embodiments, the illustrated acts orevents may be subdivided into multiple acts or events, which may becarried out at separate times or concurrently with other acts orsub-acts. In some embodiments, some illustrated acts or events may beomitted, and other un-illustrated acts or events may be included.

At step S201, a first 2-D material layer is formed over a substrate.FIGS. 12A and 12B illustrate a perspective view and a cross-sectionalview of some embodiments corresponding to act in step S201.

At step S202, a second 2-D material layer is formed over the first 2-Dmaterial layer. FIGS. 13A and 13B illustrate a perspective view and across-sectional view of some embodiments corresponding to act in stepS202.

At step S203, source/drain metals are formed over the second 2-Dmaterial layer. FIGS. 14A and 14B illustrate a perspective view and across-sectional view of some embodiments corresponding to act in stepS203.

At step S204, the second 2-D material layer is patterned. FIGS. 15A and15B illustrate a perspective view and a cross-sectional view of someembodiments corresponding to act in step S204.

At step S205, a first dielectric layer is formed over the substrate byusing a physical deposition. FIGS. 16A and 16B illustrate a perspectiveview and a cross-sectional view of some embodiments corresponding to actin step S205.

At step S206, a second dielectric layer is formed over the substrate byusing a chemical deposition. FIGS. 17A and 17B illustrate a perspectiveview and a cross-sectional view of some embodiments corresponding to actin step S206.

At step S207, a gate electrode is formed over the second dielectriclayer, and an ILD layer and interconnection structures are formed overthe substrate. FIGS. 18A and 18B illustrate a perspective view and across-sectional view of some embodiments corresponding to act in stepS207.

Based on the above discussion, it can be seen that the presentdisclosure offers advantages. It is understood, however, that otherembodiments may offer additional advantages, and not all advantages arenecessarily disclosed herein, and that no particular advantages isrequired for all embodiments. One advantage is that by employing anadditional stay time for a precursor in an ALD cycle for forming anoxide layer over a 2-D material surface, and by forming the oxide layerwith a greater thickness, the uniformity of the oxide layer over the 2-Dmaterial surface can be improved. Another advantage is that by using apre-oxide deposition to form an oxide layer may improve the coverage ofthe composite dielectric layer over a 2-D material surface. Furthermore,by combining a physical deposition and a chemical deposition, it ispossible to avoid the issue of precursor distribution on a 2-D materialsurface with the help of physically deposited thin oxide layer, andstill obtain a flat dielectric layer through the chemical deposition.Yet another advantage is that by forming a 2-D material conductive layerserving as source/drain electrode over a 2-D material semiconductorlayer, the contact resistance between the 2-D material semiconductorlayer and the source/drain electrode may be reduced, which will improvethe device performance.

In some embodiments of the present disclosure, a method includes forminga 2-D material semiconductor layer over a substrate; formingsource/drain electrodes covering opposite sides of the 2-D materialsemiconductor layer, while leaving a portion of the 2-D materialsemiconductor layer exposed by the source/drain electrodes; forming afirst gate dielectric layer over the portion of the 2-D materialsemiconductor layer by using a physical deposition process; forming asecond gate dielectric layer over the first gate dielectric layer byusing a chemical deposition process, in which a thickness of the firstgate dielectric layer is less than a thickness of the second gatedielectric layer; and forming a gate electrode over the second gatedielectric layer.

In some embodiments of the present disclosure, a method includes forminga 2-D material semiconductor layer over a substrate; formingsource/drain electrodes covering opposite sides of the 2-D materialsemiconductor layer, while leaving a portion of the 2-D materialsemiconductor layer exposed by the source/drain electrodes; forming afirst gate dielectric layer over the portion of the 2-D materialsemiconductor layer by using an atomic layer deposition (ALD) process;and forming a gate electrode over the first gate dielectric layer. TheALD process includes at least one ALD cycle each including injecting afirst precursor into an ALD chamber for a first duration; haltinginjecting the first precursor into an ALD chamber; purging the firstprecursor in the ALD chamber; injecting a second precursor into the ALDchamber for a second duration; halting injecting the second precursorinto the ALD chamber; and purging the second precursor in the ALDchamber, in which a non-zero time duration is between halting injectingthe second precursor and purging the second precursor.

In some embodiments of the present disclosure, a semiconductor deviceincludes a substrate, a 2-D material semiconductor layer, source/drainelectrodes, a first gate dielectric layer, a gate electrode. The 2-Dmaterial semiconductor layer is over the substrate. The source/drainelectrodes cover opposite sides of the first 2-D material, in which eachof the source/drain electrodes includes a 2-D material semimetal layerand a metal over the 2-D material semimetal layer. The first gatedielectric layer covers the 2-D material semiconductor layer and thesource/drain electrodes. The gate electrode is over the first gatedielectric layer.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A semiconductor device, comprising: a substrate;a 2-D material semiconductor layer over the substrate; source/drainelectrodes covering opposite sides of the 2-D material semiconductorlayer, wherein each of the source/drain electrodes comprises a 2-Dmaterial semimetal layer and a metal over the 2-D material semimetallayer; a first gate dielectric layer covering the 2-D materialsemiconductor layer and the source/drain electrodes; and a gateelectrode over the first gate dielectric layer.
 2. The semiconductordevice of claim 1, wherein the 2-D material semimetal layer is thinnerthan the metal.
 3. The semiconductor device of claim 1, wherein thefirst gate dielectric layer is in contact with the 2-D materialsemimetal layer of the source/drain electrodes.
 4. The semiconductordevice of claim 1, further comprising a second gate dielectric layerbetween the 2-D material semiconductor layer and the first gatedielectric layer, and the first gate dielectric layer is thicker thanthe second gate dielectric layer.
 5. The semiconductor device of claim1, wherein a thickness of the first gate dielectric layer is in a rangefrom about 5 nm to about 30 nm.
 6. The semiconductor device of claim 1,further comprising 2-D material layers in contact with the oppositesides of the 2-D material semiconductor layer, wherein the source/drainelectrodes are over the 2-D material layers, respectively.
 7. Thesemiconductor device of claim 6, wherein the 2-D material layers aremade of graphene.
 8. A semiconductor device, comprising: a substrate; a2-D material semiconductor layer over the substrate; 2-D material layerscovering opposite sides of the 2-D material semiconductor layer, whereinthe 2-D material layers are made of graphene; source/drain electrodesover the 2-D material layers, respectively; a first gate dielectriclayer covering the 2-D material semiconductor layer and the source/drainelectrodes; and a gate electrode over the first gate dielectric layer.9. The semiconductor device of claim 8, wherein the 2-D materialsemiconductor layer is made of transition metal dichalcogenide (TMD).10. The semiconductor device of claim 8, further comprising a secondgate dielectric layer over the first gate dielectric layer, wherein thegate electrode is in contact with a top surface of the second gatedielectric layer.
 11. The semiconductor device of claim 10, wherein thesecond gate dielectric layer is thicker than the first gate dielectriclayer.
 12. The semiconductor device of claim 10, wherein a bottomsurface of the gate electrode is higher than a topmost end of the firstgate dielectric layer.
 13. The semiconductor device of claim 10, whereinthe first gate dielectric layer and the second gate dielectric layer aremade of a same material.
 14. The semiconductor device of claim 8,wherein each of the source/drain electrodes comprises a 2-D materialsemimetal layer and a metal over the 2-D material semimetal layer.
 15. Asemiconductor device, comprising: a substrate; a 2-D materialsemiconductor layer over the substrate; source/drain electrodes coveringopposite sides of the 2-D material semiconductor layer, wherein each ofthe source/drain electrodes comprises a 2-D material semimetal layer anda metal over the 2-D material semimetal layer; a first gate dielectriclayer covering the 2-D material semiconductor layer and the source/drainelectrodes; a second gate dielectric layer over the first gatedielectric layer; and a gate electrode over the second gate dielectriclayer.
 16. The semiconductor device of claim 15, wherein the second gatedielectric layer is thicker than the first gate dielectric layer. 17.The semiconductor device of claim 15, wherein a bottom surface of thegate electrode is higher than a topmost end of the first gate dielectriclayer.
 18. The semiconductor device of claim 15, wherein the second gatedielectric layer has a flat top surface profile, while the first gatedielectric layer has a stepped top surface profile.
 19. Thesemiconductor device of claim 15, further comprising 2-D material layersin contact with the opposite sides of the 2-D material semiconductorlayer, wherein the source/drain electrodes are over the 2-D materiallayers, respectively.
 20. The semiconductor device of claim 19, whereinthe 2-D material layers are made of graphene.